1. Technical Field
The present invention relates to a liquid crystal display, and more particularly to system for driving a liquid crystal display that is capable of automatically adjusting a level of a common voltage at the point that a positive polarity gray scale level voltage and a negative polarity gray scale level voltage are supplied to a liquid crystal display panel.
2. Background
Generally, a liquid crystal display (LCD) controls light transmittance of liquid crystal cells based on video signals. An active matrix type of liquid crystal display having a switching device provided for each liquid crystal cell permits an active control of the switching device. The switching device used for the active matrix liquid crystal display mainly employs a thin film transistor (hereinafter, referred to as “TFT”) as shown in FIG. 1.
Referring to FIG. 1, the active matrix LCD converts a digital input data into an analog data voltage based on a gamma reference voltage which supplies it to a data line DL and, at the same time, supplies a scanning pulse to a gate line GL to thereby charge a liquid crystal cell Clc.
A gate electrode of the TFT is connected to the gate line GL while a source electrode thereof is connected to the data line DL. Further, a drain electrode of the TFT is connected to a pixel electrode of the liquid crystal cell Clc and to one electrode of a storage capacitor Cst.
A common electrode of the liquid crystal cell Clc is supplied with a common voltage Vcom.
The storage capacitor Cst charges a data voltage fed from the data line DL when the TFT is turned-on, thereby constantly keeping a voltage at the liquid crystal cell Clc.
If the scanning pulse is applied to the gate line GL, then the TFT is turned on to provide a channel between the source electrode and the drain electrode thereof, thereby supplying a voltage on the data line DL to the pixel electrode of the liquid crystal cell Clc. In this case, liquid crystal molecules of the liquid crystal cell have an alignment changed by an electric field between the pixel electrode and the common electrode to thereby modulate an incident light.
A configuration of the related art LCD including pixels having the above-mentioned structure will be described with reference to FIG. 2.
FIG. 2 is a block diagram showing a configuration of a general liquid crystal display.
Referring to FIG. 2, a general liquid crystal display 100 includes a liquid crystal display panel 110 provided with a thin film transistor (TFT) for driving the liquid crystal cell Clc at an intersection of data lines DL1 to DLm and gate lines GL1 to GLn crossing each other, a data driver 120 for supplying a data to the data lines DL1 to DLm of the liquid crystal display panel 110, a gate driver 130 for supplying a scanning pulse to the gate lines GL1 to GLn of the liquid crystal display panel 110, a gamma reference voltage generator 140 for generating a gamma reference voltage to supply it to the data driver 120, a backlight assembly 150 for irradiating a light onto the liquid crystal display panel 110, an inverter 160 for applying an alternating current voltage and a current to the backlight assembly 150, a common voltage generator 170 for generating a common voltage Vcom to supply it to the common electrode of the liquid crystal cell Clc of the liquid crystal display panel 110, a gate driving voltage generator 180 for generating a gate high voltage VGH and a gate low voltage VGL to supply them to the gate driver 130, and a timing controller 190 for controlling the data driver 120 and the gate driver 130.
The liquid crystal display panel 110 has a liquid crystal injected between two glass substrates. On the lower glass substrate of the liquid crystal display panel 110, the data lines DL1 to DLm and the gate lines GL1 to GLn perpendicularly cross each other. Each intersection between the data lines DL1 to DLm and the gate lines GL1 to GLn is provided with the TFT. The TFT supplies data on the data lines DL1 to DLm to the liquid crystal cell Clc in response to the scanning pulse. The gate electrode of the TFT is connected to the gate lines GL1 to GLn while the source electrode thereof is connected to the data line DL1 to DLm. Further, the drain electrode of the TFT is connected to the pixel electrode of the liquid crystal cell Clc and to the storage capacitor Cst.
The TFT is turned-on in response to the scanning pulse applied, via the gate lines GL1 to GLn, to the gate terminal thereof. Upon turning-on of the TFT, a video data on the data lines DL1 to DLm is supplied to the pixel electrode of the liquid crystal cell Clc.
The data driver 120 supplies a data to the data lines DL1 to DLm in response to a data driving control signal DDC supplied from the timing controller 190. Further, the data driver 120 samples and latches a digital video data RGB fed from the timing controller 190, and then converts it into an analog data voltage capable of expressing a gray scale level at the liquid crystal cell Clc of the liquid crystal display panel 110 on the basis of a gamma reference voltage from the gamma reference voltage generator 140, thereby supplying it the data lines DL1 to DLm.
The gate driver 130 sequentially generates a scanning pulse, that is, a gate pulse in response to a gate driving control signal GDC and a gate shift clock GSC supplied from the timing controller 190 to supply them to the gate lines GL1 to GLn. The gate driver 130 determines a high level voltage and a low level voltage of the scanning pulse based on the gate high voltage VGH and the gate low voltage VGL supplied from the gate driving voltage generator 180.
The gamma reference voltage generator 140 receives a high-level supply voltage VDD to generate a positive gamma reference voltage and a negative gamma reference voltage and outputs them to the data driver 120.
The backlight assembly 150 is provided at the rear side of the liquid crystal display panel 110, and is radiated by an alternating current voltage and a current supplied from the inverter 160 to irradiate a light onto each pixel of the liquid crystal display panel 110.
The inverter 160 converts a square wave signal generated at the interior thereof into a triangular wave signal and then compares the triangular wave signal with a direct current power voltage VCC supplied from the system, thereby generating a burst dimming signal proportional to a result of the comparison. If the burst dimming signal is determined in accordance with the rectangular wave signal at the interior of the inverter 160, then a driving integrated circuit (IC) (not shown), for controlling a generation of the AC voltage and current within the inverter 160 controls a generation of AC voltage and current supplied to the backlight assembly 150 in response to the burst dimming signal.
The common voltage generator 170 receives a high-level power voltage VDD to generate a common voltage Vcom, and supplies it to the common electrode of the liquid crystal cell Clc provided at each pixel of the liquid crystal display panel 110.
The gate driving voltage generator 180 is supplied with a high-level power voltage VDD to generate the gate high voltage VGH and the gate low voltage VGL, and supplies them to the gate driver 130. Herein, the gate driving voltage generator 180 generates a gate high voltage VGH, more than a threshold voltage of the TFT provided at each pixel of the liquid crystal display panel 110, and a gate low voltage VGL less then the threshold voltage of the TFT. The gate high voltage VGH and the gate low voltage VGL generated in this manner are used for determining a high level voltage and a low level voltage of the scanning pulse generated by the gate driver 130, respectively.
The timing controller 190 supplies a digital video data RGB from a digital video card (not shown) to the data driver 120 and, at the same time, generates a data driving control signal DCC and a gate driving control signal GDC using horizontal/vertical synchronizing signals H and V in response to a clock signal CLK to supply them to the data driver 120 and the gate driver 130, respectively. Herein, the data driving control signal DDC includes a source shift clock SSC, a source start pulse SSP, a polarity control signal POL and a source output enable signal SOE, etc. The gate driving control signal GDC includes a gate start pulse GSP and a gate output enable signal GOE, etc.
An operation of the above-mentioned liquid crystal display will be described with reference to signal characteristics shown in FIG. 3.
First, if the gate driver 130 supplies a gate pulse A1 to the gate lines GL1 to GLn to drive a thin film transistor of each pixel, then the data driver 120 converts a digital data input from the timing controller 190 into an analog data A2 to supply it to a plurality of data lines DL1 to DLm. In this case, an analog data A2 is supplied in a square wave type which a positive polarity (+) section and a negative polarity (−) section bisected in such a manner to have a symmetry each other shown in FIG. 3, but substantially a positive polarity gray scale level voltage A3 and a negative polarity gray scale level voltage A4 are changed by an external environment and an interior resistance to not be supplied a square wave type and to generate a drop.
In a phenomenon in which a gray scale level voltage is dropped, a positive polarity gray scale level voltage and a negative polarity gray scale level voltage are all dropped, and a drop voltage ΔVp_P of a positive polarity gray scale level voltage and a drop voltage ΔVp_N of a negative polarity gray scale level voltage are the same as each other.
As described above, even though a positive polarity gray scale level voltage and a negative polarity gray scale level voltage are all dropped, a common voltage Vcom is always constantly supplied, so that a charging amount of a liquid crystal cell by a positive polarity gray scale level voltage is reduced as a magnitude of a drop voltage ΔVp_P while a charging amount of a liquid crystal cell by a negative polarity gray scale level voltage is increased as a magnitude of a drop voltage ΔVp_N. As a result, a charging amount of a positive polarity gray scale level voltage and a charging amount of a negative polarity gray scale level voltage are randomized, so that a flicker is generated on the screen.